Resonant clock distribution networks have been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance.
In practice, digital devices are often specified and designed to operate at multiple clock frequencies. For example, a high-performance microprocessor may be designed to operate at multiple clock frequencies ranging from 100 MHz to 3 GHz. The technique of operating a clock signal at different clock frequencies over time is commonly referred to as frequency scaling and is motivated by the need to reduce power consumption in semiconductor devices. Power consumption in digital semiconductor devices grows in proportion with the rate at which these devices switch between their digital values. When performance requirements decrease, this rate can be reduced by reducing the frequency of the clock signal, thereby reducing power consumption.
The operation of clock signals at more than a single frequency also arises in the context of device binning, that is, the practice of selling at a premium a device that, due to manufacturing variations, is capable of operating at a higher peak clock frequency than another device of identical design and functionality. For example, a batch of microprocessors that was fabricated on a “fast” semiconductor manufacturing corner may contain microprocessors capable of running at clock frequencies of up to 3 GHz, while an identical-in-design batch of microprocessors that was fabricated on a “typical” semiconductor manufacturing corner may contain microprocessors that can run at clock frequencies of at most 2 GHz. While of identical design, the microprocessors in the first “fast” batch can be sold at significantly higher prices, due to their better achieved performance.
The challenge with the deployment of resonant clock distribution networks in multi-frequency operation contexts is that these networks typically achieve their highest energy efficiency for a relatively narrow range of clock frequencies centered around the natural frequency of the resonant network. For clock frequencies outside this narrow range, energy efficiency degrades significantly, and to an extent that can outweigh the inherent energy advantages of resonant clocking. For example, consider a microprocessor that has been designed with a target frequency of 3 GHz, but its digital logic can only achieve a peak clock rate of 2 GHz after manufacturing. In a non-resonant clock implementation of the microprocessor, the clock network can be operated at 2 GHz, consuming power in proportion to its 2 GHz operating frequency. In a resonant clock design, however, if the resonant clock network operates at 2 GHz, instead of its natural frequency of 3 GHz, its power consumption can significantly exceed the power consumption of the non-resonant design at 2 GHz.
In addition to excessive power consumption, when a resonant clock network operates away from its natural frequency, the shape of the clock waveform is increasingly deformed, as the mismatch between the natural and the operating frequency increases. In extreme situations, the peak clock frequency after manufacturing may be so far from the natural frequency of the resonant clock network that the clock waveform at the peak clock frequency becomes deformed to such an extent that incorrect operation of the clocked elements results, and the function of the overall device becomes incorrect.
It is possible to address the above challenges in a number of straightforward yet impractical ways. One such approach is to enable the adjustment of the natural frequency by providing for the selective introduction of capacitance to the resonant clock network. Since the energy efficiency of the resonant clock network decreases as its capacitance increases, adjusting the natural frequency by introducing capacitance compromises power savings at lower operating frequencies. Moreover, the area overhead of the spare capacitance may be prohibitively high.
Another approach to the adjustment of the natural frequency is the deployment of series or parallel combinations of multiple distinct inductors that can be selectively engaged. In general, however, the use of multiple distinct inductors results in potentially prohibitive area overheads.
An alternative approach to addressing the above challenges is to design resonant clock drivers that are capable of also operating in conventional (i.e., non-resonant) mode. In this approach, the resonant clock network can be operated at any clock frequency in conventional mode. However, these derivers typically rely on the introduction of a switch in series to the inductor and the clock load, thus increasing overall resistance of the resonant clock network and degrading its energy efficiency when operating in resonant mode.
Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for_Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007; “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. In all these articles, the resonant clock distribution networks are restricted to a single natural frequency. No attempt is made and no methods are proposed for operating the resonant clock networks in a way that addresses the aforementioned challenges.
Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.